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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 20211hkpc 20100603-s00007, s00009, s00010, s00012, s00013, s00014 no.a1780-1/31 * this product is licensed from silicon storage tec hnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. ver.1.03 lc87f83c8a/au lc87f8396a/au lc87f8364a/au overview the lc87f83c8a/au/96a/au/64a/au is an 8-bit etr micr ocomputer that, centered around a cpu running at a minimum bus cycle time of 74.04 ns, inte grate on a single chip a number of hard ware features such as 128k-bytes of flash rom maximum (onboard rewritable), 6k-bytes of ram maximum, onchip debugging, direct control of necessary cd mechanism and cd-dsp for car audio, in the radio reception, th e on-chip high-performance pll circuit provides a high-speed lock-up circuit to search for altern ative frequency of rds in a short time, the ability to control the c/n characteristics of a local oscillator, and the high s/n through the direct pll configuration, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two sy nchronous sio ports (with automatic bloc k transmission/reception capabilities), an asynchronous/synchronous sio port, two uart ports (full duplex), four 12-bit pwm channels, an 8-bit 10-channel ad converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. rom for each model/table ram capacity type no. flash rom (byte) ram (byte) lc87f8364a/au 64k 4k lc87f8396a/au 96k 6k lc87f83c8a/au 128k 6k features flash rom ? single 5v power supply, on-board writeable ? block erase in 128 byte units cmos ic from 128k byte, ram 6k byte on-chip 8-bit etr microcontroller orderin g numbe r : ena1780
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-2/31 minimum bus cycle time ? 74.04ns (13.5mhz) note: bus cycle time indicates the speed to read rom. minimum instruction cycle time (tcyc) ? 222ns (13.5mhz) ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units: 57 (p1n, p2n, p30 to p35, p70 to p73, p8n, pbn, pcn, si2pm, pwm0, pwm1, xt2, n=0 to 7, m=0 to 3) ports whose i/o direction can be designated in 2 bit units: 16 (pen, pfn n=0 to 7) ports whose i/o direction can be designated in 4 bit units: 8 (p0n n=0 to 7) ? normal withstand voltage input ports: 1 (xt1) ? main charge pump output ports: 1 (eo) ? sub charge pump output ports: 1 (subpd) ? am local oscillator input ports: 1 (amin) ? fm local oscillator input ports: 1 (fmin) ? high-speed, universal counter input ports: 1 (hctr) ? universal counter input ports: 1 (lctr) ? internal low voltage output ports: 1 (vreg) ? dedicated oscillator ports: 2 (cf1, cf2) ? reset pin: 1 ( res ) ? digital power pins: 6 (v ss n, v dd n n=1, 2, 4) ? analogue power pins: 2 (av ss n, av dd ) timers ? timer 0: 16-bit programmable timer/counter with capture register mode 0: 8-bit programmable timer with an 8-bit pr ogrammable prescaler (with tw o 8-bit capture registers) 2 channels mode 1: 8-bit programmable timer with an 8-bit pr ogrammable prescaler (with tw o 8-bit capture registers) + 8-bit programmable counter (with two 8-bit capture registers) mode 2: 16-bit programmable timer with an 8-bit progr ammable prescaler (with two 16-bit capture registers) mode 3: 16-bit programmable counter (with 2 16-bit capture registers) ? timer 1: 16-bit programmable timer/counter that support pwm/ toggle output mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle outputs) + 8-bit programmable timer/counter (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit programmable timer with a 6-bit prescaler ? timer 5: 8-bit programmable timer with a 6-bit prescaler ? timer 6: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768 khz crystal oscillator), cycl e clock (tcyc), and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes. high speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (when high-speed clock counter is used, timer 0 cannot be used). 2) can generate output real time.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-3/31 sio: 3 channels ? sio 0: 8 bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (4/3 to 512/3 tcyc transfer clock cycle) 3) automatic continuous data transmission (1 to 256 bits) ? sio 1: 8 bit asynchronous/s ynchronous serial interface mode 0: synchronous 8-bit serial i/o (2 to or 3 to wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio2: 8 bit synchronous serial interface 1) lsb first mode 2) built-in 3-bit baudrate generator (4/3 to 512/3 tcyc transfer clock cycle) 3) automatic continuous data transmission (1 to 32 bytes) uart: 2 channels 1) full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tcyc) ad converter: 8 bits 10 channels pwm: multifrequency 12-bit pwm 4 channels remote control receiver noise filtering functio n (sharing pins with p73, int3, and t0in) 1) noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc 2) the noise filtering function is available for the int3, t0 in, or t0hcp signal at p73. when p73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable interrupts ? 29 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer (bt0, 1) 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive/uart2 receive 8 0003bh h or l sio1/sio2/uart 1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7/pwm4, pwm5 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? the base timers are two interrupt sources of bt0 and bt1, it is one interrupt source by pwm0 and 1, it is one interrupt source by pwm4 and 5.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-4/31 subroutine stack levels ? 3072 levels maximum (1/2 of capacity of ram, the stack is allocated in ram.) high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) oscillation circuits and pll ? rc oscillator circuit (internal): for system clock ? main xt crystal oscillator circuit: for system clock with internal rf, rd ? sub xt crystal oscillator circuit: for time-of-day cl ock, for low-speed system clock with internal rf and external rd ? multifrequency rc oscillator circuit (internal): for system clock ? pll circuit (internal): for am/fm tuner system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 222ns, 444ns, 888ns, 1.78 s, 3.55 s, 7.10 s, 14.2 s, 28.4 s, and 56.8 s. pll block ? twelve reference frequencies when main xt is 13.5mhz: 1khz, 3khz, 3.125khz, 5khz, 6.25khz, 9khz, 10khz, 12.5khz, 25khz, 30khz, 50khz, and 100khz ? range of input frequency 1) amin: 0.5 to 40mhz 2) fmin: 10 to 150mhz 3) hctr: 0.4 to 12mhz 4) lctr: 100 to 500khz ? supports dead zone control. ? built-in unlock detection circuit. universal counter ? this 20-bit counter can be us ed for frequency measurement. standby function ? halt mode: halts instruction execution while allowi ng the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by system reset, detection vdet0 or occurrence of interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the main xt crystal oscillators, rc, and sub xt crystal oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) voltage descent detection (vdet1) (3) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (4) having an interrupt source established at port 0. ? x'tal hold mode: suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) the main xt crystal oscillators, and rc oscillators automatically stop operation. 2) the state of crystal oscillation established when the hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) voltage descent detection (vdet0) (3) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (4) having an interrupt source established at port 0. (5) having an interrupt source established in the base timer circuit.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-5/31 reset ? external reset ? voltage descent detection (vdet0, vdet1) reset circuit (internal) onchip debugging function ? permits software debugging with the te st device installed on the target board. shipping form ? qip100e (lead free product) flash rom version ? lc87f83c8a/96a/64a ? LC87F83C8AU/96au/64au (user writing)
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-6/31 absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 4, av dd v dd 1=v dd 2=v dd 4 =av dd -0.3 +6.5 input voltage v i (1) cf1, xt1, amin, fmin, hctr, lctr -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2 ports 3, 7, 8 ports b, c, e, f si2p0 to si2p3 pwm0, pwm1, xt2 -0.3 v dd +0.3 output voltage v o (1) eo, subpd -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 ports 71 to 73 ports b, c, e, f si2p0 to si2p3 cmos output select per 1 application pin -10 ioph(2) pwm0, pwm1 per 1 application pin. -20 peak output current ioph(3) eo, subpd per 1 application pin. -5 iomh(1) ports 0, 1, 2, 3 ports 71 to 73 ports b, c, e, f si2p0 to si2p3 cmos output select per 1 application pin -7.5 iomh(2) pwm0, pwm1 per 1 application pin. -15 average output current (note 1-1) iomh(3) eo, subpd per 1 application pin. -3 ioah(1) p71 to p73 total of all applicable pins -25 ioah(2) pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -25 ioah(3) ports 0 total of all applicable pins -25 ioah(4) port 0 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -45 ioah(5) ports 2, 3, b total of all applicable pins -25 ioah(6) ports c total of all applicable pins -25 ioah(7) ports 2, 3, b, c total of all applicable pins -45 ioah(8) ports f total of all applicable pins -25 ioah(9) ports 1, e total of all applicable pins -25 ioah(10) ports 1, e, f total of all applicable pins -45 high level output current total output current ioah(11) eo, subpd total of all applicable pins -10 ma note 1-1: average output current is av erage of current in 100ms interval. continued on next page.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-7/31 continued from preceding page. specification parameter symbol pins /remarks conditions v dd [v] min typ max unit iopl(1) ports 0, 1, 2, 3, 8 ports b, c, e, f si2p0 to si2p3 xt2 per 1 application pin. 10 iopl(2) pwm0, pwm1 per 1 application pin. 20 peak output current iopl(3) eo, subpd per 1 application pin. 5 ioml(1) ports 0, 1, 2, 3, 7 ports 8, b, c, e, f si2p0 to si2p3 xt2 per 1 application pin. 7.5 ioml(2) pwm0, pwm1 per 1 application pin. 20 average output current (note 1-1) ioml(3) eo, subpd per 1 application pin. 5 ioal(1) port 7, xt2 total of all applicable pins 25 ioal(2) port 8 total of all applicable pins 25 ioal(3) ports 7, 8, xt2 total of all applicable pins 45 ioal(4) pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 25 ioal(5) port 0 total of all applicable pins 25 ioal(6) port 0 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 45 ioal(7) ports 2, 3, b total of all applicable pins 25 ioal(8) ports c total of all applicable pins 25 ioal(9) ports 2, 3, b, c total of all applicable pins 45 ioal(10) port f total of all applicable pins 25 ioal(11) ports 1, e total of all applicable pins 25 ioal(12) ports 1, e, f total of all applicable pins 45 low level output current total output current ioal(13) eo, subpd total of all applicable pins 10 ma maximum power consumption pd max qip100e ta = -40 to +85 c 400 mw operating temperature range topr -40 +85 c storage temperature range tstg -45 +125 c note 1-1: average output current is av erage of current in 100ms interval.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-8/31 recommended operating range at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit pll operation 4.5 5.0 5.5 operating supply voltage v dd (1) v dd 1=v dd 2=v dd 4 =av dd cpu operation 3.0 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 4 =av dd ram and register contents in hold mode. 1.0 5.5 v ih (1) ports 1, 2 si2p0 to 3 p71 to p73 p70 port input/ interrupt side 3.0 to 5.5 0.35v dd +0.7 v dd v ih (2) ports 0, 3, 8 ports b, c, e, f pwm0, pwm1 3.0 to 5.5 0.3v dd +0.7 v dd v ih (3) port70 watchdog timer side 3.0 to 5.5 0.9v dd v dd high level input voltage v ih (4) xt1, xt2, res when xt1 and xt2 general purpose input 3.0 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) ports 1, 2 si2p0 to 3 p71 to p73 p70 port input/ interrupt side 3.0 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) ports 0, 3, 8 ports b, c, e, f pwm0, pwm1 3.0 to 4.0 v ss 0.2v dd v il (5) port70 watchdog timer side 3.0 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) xt1, xt2, res when xt1 and xt2 general purpose input 3.0 to 5.5 v ss 0.25v dd v v in (1) fmin, amin, hctr, lctr excluding cf ability setting=?00? 4.5 to 5.5 0.04 1.5 v in (2) fmin, amin, hctr cf ability setting=?00? 4.5 to 5.5 0.07 1.5 input amplitude v in (3) fmin, lctr cf ability setting=?00? 4.5 to 5.5 0.04 1.5 vrms fin(1) fmin: v in (1) 4.5 to 5.5 10 150 fin(2) fmin: v in (2) 4.5 to 5.5 10 50 fin(3) fmin: v in (3) 4.5 to 5.5 50 150 fin(4) amin(h): v in (1) v in (2) 4.5 to 5.5 2 40 fin(5) amin(l): v in (1) v in (2) 4.5 to 5.5 0.5 10 fin(6) hctr: v in (1) v in (2) 4.5 to 5.5 0.4 12 mhz input frequency fin(7) lctr: v in (1) v in (3) 4.5 to 5.5 100 500 khz instruction cycle time (note 2-1) tcyc 3.0 to 5.5 0.222 s fmcf(1) cf1, cf2 13.5mhz crystal oscillation. 3.0 to 5.5 13.5 fmrc internal rc oscillation 3.0 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 3.0 to 5.5 16 mhz oscillation frequency range fsx?tal xt1, xt2 32.768khz crystal oscillation. 3.0 to 5.5 32.768 khz note 2-1: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-9/31 electrical characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2 ports 3, 7, 8 ports b, c, e, f si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v dd (including the off-leak current of the output tr.) 3.0 to 5.5 1 i ih (2) xt1, xt2 using as an input port v in =v dd 3.0 to 5.5 1 i ih (3) cf1 v in =v dd 3.0 to 5.5 1 5 15 high level input curre i ih (4) fmin, amin, hctr, lctr v in =v dd 4.5 to 5.5 30 i il (1) ports 0, 1, 2 ports 3, 7, 8 ports b, c, e, f si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v dd (including the off-leak current of the output tr.) 3.0 to 5.5 -1 i il (2) xt1, xt2 using as an input port v in =v ss 3.0 to 5.5 -1 i il (3) cf1 v in =v ss 3.0 to 5.5 -15 -5 -1 low level input current i il (4) fmin, amin, hctr, lctr v in =v ss 4.5 to 5.5 -30 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) ports 0, 1, 2, 3 ports b, c, e, f ports 71, 72, 73 si2p0 to si2p3 i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (4) pwm0, pwm1 p30, p31(pwm4, 5 output mode) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (5) eo, subpd i oh =-500 a 4.5 to 5.5 v dd -1 v ol (1) i ol =1.0ma 4.5 to 5.5 1.0 v ol (2) ports 0, 1, 2, 3 ports b, c, e, f ports 71, 72, 73 si2p0 to si2p3 i ol =0.4ma 3.0 to 5.5 0.4 v ol (3) i ol =10ma 4.5 to 5.5 1.5 v ol (4) pwm0, pwm1 i ol =1.6ma 3.0 to 5.5 0.4 v ol (5) ports 70, 8, xt2 i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (6) eo, subpd i ol =500 a 4.5 to 5.5 1.0 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistation rpu(2) ports 0, 1, 2, 3 port 7 ports b, c, e, f v oh =0.9v dd 3.0 to 5.5 15 35 150 k hysteresis voltage vhys res ports 1, 2, 7 si2p0 to si2p3 3.0 to 5.5 0.1v dd v pin capacitance cp all pins ? for pins other than that under test: v in =v ss ? f=1mhz ? ta=25c 3.0 to 5.5 10 pf vdet0 ? excluding the hold mode 3.0 3.3 3.6 power down detection voltage vdet1 v dd 1 ? hold mode 1.1 1.6 2.1 v
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-10/31 serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) ? see fig. 2. 1 tsckha(1a) ? continuous data transmission/reception mode ? sio2 is not in use simultaneous. ? see fig. 2. ? (note 4-1-2) 4 input clock high level pulse width tsckha(1b) sck0(p12) ? continuous data transmission/reception mode ? sio2 is in use simultaneous. ? see fig. 2. ? (note 4-1-2) 3.0 to 5.5 6 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected. ? see fig. 2. 1/2 tsck tsckha(2a) ? continuous data transmission/reception mode ? sio2 is not in use simultaneous. ? cmos output selected. ? see fig. 2. tsckh(2) +2tcyc tsckh(2) +(10/3)tcyc serial clock output clock high level pulse width tsckha(2b) sck0(p12) ? continuous data transmission/reception mode ? sio2 is in use simultaneous. ? cmos output selected. ? see fig. 2. 3.0 to 5.5 tsckh(2) +2tcyc tsckh(2) +(16/3)tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p11), sb0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 2. 3.0 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode. ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tdd0(3) si0(p11), sb0(p11) ? (note 4-1-3) 3.0 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 2.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-11/31 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) ? see fig. 2. 3.0 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected. ? see fig. 2. 3.0 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si1(p14), sb1(p14) ? must be specified with respect to rising edge of sioclk ? see fig. 2. 3.0 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 2. 3.0 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-12/31 3. sio2 serial i/o characteristics (note 4-3-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(5) 2 low level pulse width tsckl(5) 1 tsckh(5) ? see fig. 2. 1 tsckha(5a) ? continuous data transmission/reception mode of sio0 is not in use simultaneous. ? see fig. 2. ? (note 4-3-2) 4 input clock high level pulse width tsckha(5b) sck2 (si2p2) ? continuous data transmission/reception mode of sio0 is in use simultaneous. ? see fig. 2. ? (note 4-3-2) 3.0 to 5.5 7 frequency tsck(6) 4/3 tcyc low level pulse width tsckl(6) 1/2 tsckh(6) ? cmos output selected. ? see fig. 2. 1/2 tsck tsckha(6a) ? continuous data transmission/reception mode of sio0 is not in use simultaneous. ? cmos output selected. ? see fig. 2. tsckh(6) +(5/3)tcyc tsckh(6) +(10/3)tcyc serial clock output clock high level pulse width tsckha(6b) sck2 (si2p2) sck2o (si2p3) ? continuous data transmission/reception mode of sio0 is in use simultaneous. ? cmos output selected. ? see fig. 2. 3.0 to 5.5 tsckh(6) +(5/3)tcyc tsckh(6) +(19/3)tcyc tcyc data setup time tsdi(3) 0.03 serial input data hold time thdi(3) si2(si2p1), sb2(si2p1) ? must be specified with respect to rising edge of sioclk ? see fig. 2. 3.0 to 5.5 0.03 serial output output delay time tdd0(5) so2(si2p0), sb2(si2p1) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 2. 3.0 to 5.5 (1/3)tcyc +0.05 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input, a time from si2run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-13/31 pulse input conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 3.0 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 3.0 to 5.5 2 tpih(3) tpil(3) int3(p73) (the noise rejection clock is selected to 1/32.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 3.0 to 5.5 64 tpih(4) tpil(4) int3(p73) (the noise rejection clock is selected to 1/128.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 3.0 to 5.5 256 tcyc high/low level pulse wid tpil(5) res reset acceptable 3.0 to 5.5 200 s ad converter characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 6-1) 3.0 to 5.5 1.5 lsb ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 3.0 to 5.5 7.104(tcyc= 0.222 s) conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 3.0 to 5.5 14.21(tcyc= 0.222 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p80) to an7(p87) an8(p70) an9(p71) vain=v ss 3.0 to 5.5 -1 a note 6-1: the quantization error ( 1/2 lsb) is excluded from the absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. v dd res internal regulator stabilization time must be 10ms (max.) or more. fi g ure powe r -on time reset timin g
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-14/31 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 8.0 10.0 iddop(2) ? fmcf=13.5mhz crystal oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 13.5mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 3.0 to 4.5 6.0 8.0 iddop(3) 4.5 to 5.5 0.8 1.2 iddop(4) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 3.0 to 4.5 0.6 1.0 iddop(5) 4.5 to 5.5 0.8 2.0 iddop(6) ? fmcf=0hz (oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? internal rc oscillation stopped ? system clock set to 1mhz with frequency variable rc oscillation ? 1/2 frequency division ratio. 3.0 to 4.5 0.5 1.5 ma iddop(7) 4.5 to 5.5 300 500 iddop(8) ? fmcf=0hz (oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 3.0 to 4.5 250 450 a normal mode consumption current (note 7-1) iddop(9) v dd 1 =v dd 2 =v dd 4 =av dd ? fmcf=13.5mhz crystal oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 13.5mhz side ? internal rc oscillation operation ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. ? fm amp on 130mhz reception ? hctr amp on if count 10.7mhz 4.5 to 5.5 15.0 20.0 ma note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. general-purpose i/o port "l" output when the above-mentioned data is measured however, the p0 port is an input setting because of the mode setting continued on next page.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-15/31 continued from preceding page. specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddhalt(1) 4.5 to 5.5 2.0 3.0 iddhalt(2) ? halt mode ? fmcf=13.5mhz crystal oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 13.5mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 3.0 to 4.5 1.8 2.5 iddhalt(3) 4.5 to 5.5 0.5 1.0 iddhalt(4) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 3.0 to 4.5 0.3 0.8 iddhalt(5) 4.5 to 5.5 1.0 2.0 iddhalt(6) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? internal rc oscillation stopped ? system clock set to 1mhz with frequency variable rc oscillation ? 1/2 frequency division ratio. 3.0 to 4.5 0.8 1.5 ma iddhalt(7) 4.5 to 5.5 250 500 halt mode consumption current (note 7-1) iddhalt(8) v dd 1 =v dd 2 =v dd 4 =av dd ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 3.0 to 4.5 200 400 iddhold(1) 4.5 to 5.5 1.5 20.0 current drain during hold mode iddhold(2) v dd 1 ? hold mode 3.0 to 4.5 1.0 18.0 iddhold(3) 4.5 to 5.5 150 300 current drain during time- base clock hold mode iddhold(4) v dd 1 ? timer hold mode ? fmx'tal=32.768khz by crystal oscillation mode 3.0 to 4.5 100 200 iddclock(1) 4.5 to 5.5 250 500 current drain during intermittent for clock mode iddclock(2) v dd 1 =v dd 2 =v dd 4 =av dd ? intermittent for clock mode ? each 500ms is shifted to a normal mode, and 20 steps are executed. ? fmcf=0hz (oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 3.0 to 4.5 200 400 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. general-purpose i/o port "l" output when the above-mentioned data is measured however, the p0 port is an input setting because of the mode setting
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-16/31 f-rom write characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current including 3.0 to 5.5 25 40 ma programming time tfw(1) ? 128-byte programming ? erasing current including ? time for setting up 128 byte data is excluded. 3.0 to 5.5 22.5 35 ms uart(full duplex) operating conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 4 = av ss = 0v specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit clock rate ubr, ubr2 utx1(p32), rtx1(p33), utx2(p33), rtx2(p34) 3.0 to 5.5 16/3 8192/3 tcyc data length: 7, 8, and 9 bits ( lsb first ) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: non example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) stop bit start bit transmit data (lsb first) start of transmission end of transmission ubr, ubr2 stop bit received data (lsb first) ubr, ubr2 start of reception start bit end of reception
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-17/31 package dimensions unit : mm (typ) 3151a sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-18/31 pin assignment sanyo: qip100e (lead free product) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 7 9 7 8 77 7 6 75 74 7 3 7 2 7 1 7 0 69 68 6 7 66 6 5 6 4 63 62 61 60 5 9 5 8 57 5 6 55 54 5 3 5 2 5 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pb6 pb7 p35/urx2 p34/utx2 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p27/int5/t1in/t0lcp/t0hcp p26/int5/t1in/t0lcp/t0hcp p25/int5/t1in/t0lcp/t0hcp p24/int5/t1in/t0lcp/t0hcp/int7/t0hcp1 p23/int4/t1in/t0lcp/t0hcp p22/int4/t1in/t0lcp/t0hcp p21/int4/t1in/t0lcp/t0hcp p20/int4/t1in/t0lcp/t0hcp/int6/t0lcp1 p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck2o si2p2/sck2 pb5 pb4 pb3 pb2 pb1 pb0 vreg av ss av dd fmin amin hctr lctr eo subpd pc0 pc1 pc2 pc3 pc4 pc5/dbgp0 pc6/dbgp1 pc7/dbgp2 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/t0lcp p73/int3/t0in/t0hcp res xt1 xt2 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz si2p1/si2/sb2 si2p0/so2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd 4 v ss 4 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 lc87f83c8a/au lc87f8396a/au lc87f8364a/au top view
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-19/31 pin no. name pin no. name 1 pc5/dbgp0 51 si2p2/sck2 2 pc6/dbgp1 52 si2p3/sck2o 3 pc7/dbgp2 53 pwm1 4 p70/int0/t0lcp/an8 54 pwm0 5 p71/int1/t0hcp/an9 55 v dd 2 6 p72/int2/t0in/t0lcp 56 v ss 2 7 p73/int3/t0in/t0hcp 57 p00 8 res 58 p01 9 xt1 59 p02 10 xt2 60 p03 11 v ss 1 61 p04 12 cf1 62 p05/cko 13 cf2 63 p06/t6o 14 v dd 1 64 p07/t7o 15 p80/an0 65 p20/int4/t1i n/t0lcp/t0hcp/int6/t0lcp1 16 p81/an1 66 p21/int4/t1in/t0lcp/t0hcp 17 p82/an2 67 p22/int4/t1in/t0lcp/t0hcp 18 p83/an3 68 p23/int4/t1in/t0lcp/t0hcp 19 p84/an4 69 p24/int5/t1in/t0lcp/t0hcp/int7/t0hcp1 20 p85/an5 70 p25/int5/t1in/t0lcp/t0hcp 21 p86/an6 71 p26/int5/t1in/t0lcp/t0hcp 22 p87/an7 72 p27/int5/t1in/t0lcp/t0hcp 23 p10/so0 73 p30/pwm4 24 p11/si0/sb0 74 p31/pwm5 25 p12/sck0 75 p32/utx1 26 p13/so1 76 p33/urx1 27 p14/si1/sb1 77 p34/utx2 28 p15/sck1 78 p35/urx2 29 p16/t1pwml 79 pb7 30 p17/t1pwmh/buz 80 pb6 31 pe0 81 pb5 32 pe1 82 pb4 33 pe2 83 pb3 34 pe3 84 pb2 35 pe4 85 pb1 36 pe5 86 pb0 37 pe6 87 vreg 38 pe7 88 av ss 39 v ss 4 89 av dd 40 v dd 4 90 fmin 41 pf0 91 amin 42 pf1 92 hctr 43 pf2 93 lctr 44 pf3 94 eo 45 pf4 95 subpd 46 pf5 96 pc0 47 pf6 97 pc1 48 pf7 98 pc2 49 si2p0/so2 99 pc3 50 si2p1/si2/sb2 100 pc4
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-20/31 system block diagram interrupt control standby control ir pla rom pc bus interface port 0 port 1 sio0 sio1 sio2 timer 0 timer 1 timer 4 timer 5 port 3 port 7 port 8 adc int0 to 3 noise rejection filter acc b register c register psw rar ram stack pointer watchdog timer alu pwm0 pwm1 base timer port 2 int4, 5, 6, 7 port e port f timer 6 timer 7 port b port c uart1 uart2 pwm5 pwm4 vreg operation v dd operation clock generator mainxt rc subxt mrc cf1 cf2 xt1 xt2 res regulator vreg v ss v dd
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-21/31 pin description name pin no. i/o function description option v ss 1 v ss 2 v ss 4 av ss 11 56 39 88 - ? power supply pin ? connect it with gnd no v dd 1 v dd 2 v dd 4 av dd 14 55 40 89 - ? power supply pin ? connect it with v dd no port 0 p00 p01 p02 p03 p04 p05 p06 p07 57 58 59 60 61 62 63 64 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistor can be turned on and off in 4-bit units ? hold release input ? port 0 interrupt input ? pin functions p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 p11 p12 p13 p14 p15 p16 p17 23 24 25 26 27 28 29 30 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11: sio0 data input, bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input, bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output, beeper output yes port 2 p20 p21 p22 p23 p24 p25 p26 p27 65 66 67 68 69 70 71 72 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p20: int4 input/hold reset input/time r 1 event input/timer 0l capture input/ timer 0h capture input/int6 in put/timer 0l capture 1 input p21 to p23: int4 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p24: int5 input/hold reset input/time r 1 event input/timer 0l capture input/ timer 0h capture input/int7 in put/timer 0h capture 1 input p25 to p27: int5 input/hold reset input/ timer 1 event input/timer0l capture input/ timer 0h capture input interrupt acknowledge type ? interrupt acknowledge type rising falling rising/ falling h level l level int4 int5 int6 int7 enable enable enable enable enable enable enable enable enable enable enable enable disable disable disable disable disable disable disable disable yes port 3 p30 p31 p32 p33 p34 p35 73 74 75 76 77 78 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p30: pwm4 output p31: pwm5 output p32: uart1 transmit p33: uart1 receive p34: uart2 transmit p35: uart2 receive yes continued on next page.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-22/31 continued from preceding page. name pin no. i/o function description option port 7 p70 p71 p72 p73 4 5 6 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p70: int0 input/hold release input/timer 0l capture input/output for watchdog timer/ ad converter input port p71: int1 input/hold release input/timer 0h capture input/ ad converter input port p72: int2 input/hold release input/timer 0 event input/timer0l capture input p73: int3 input with noise filter/timer 0 event input/timer 0h capture input ? interrupt acknowledge type rising falling rising/ falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable no port 8 p80 p81 p82 p83 p84 p85 p86 p87 15 16 17 18 19 20 21 22 i/o ? 8-bit i/o port (output: n-channel open drain) ? i/o specifiable in 1-bit units ? other functions p80 to p87: ad converter input port no port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 86 85 84 83 82 81 80 79 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port c pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 96 97 98 99 100 1 2 3 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units pin functions pc5 to pc7: on-chip debugger yes port e pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 31 32 33 34 35 36 37 38 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no port f pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 41 42 43 44 45 46 47 48 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no continued on next page.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-23/31 continued from preceding page. name pin no. i/o function description option sio2 si2p0 si2p1 si2p2 si2p3 49 50 51 52 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? shared functions: si2p0: sio2 data output si2p1: sio2 data input, bus input/output si2p2: sio2 clock input/output si2p3: sio2 clock output no pwm0 54 i/o ? pwm0 output port ? general-purpose i/o available no pwm1 53 i/o ? pwm1 output port ? general-purpose i/o available no res 8 i ? reset pin must connect it with v dd 1 through rc (refer to page27 figure 1) no xt1 9 i ? input terminal for 32.768khz x'tal oscillation ? shared functions: general-purpose input port must be set for input with software and connected to v ss 1 if not to be used. no xt2 10 i/o ? output terminal for 32.768khz x'tal oscillation ? shared functions: general-purpose i/o port must be set for general-purpose out put and kept open if not to be used. please connect suitable dumping resistance fo r the crystal used between the terminal when you use it as output terminal for 32.768khz x'tal oscillation. no cf1 12 i ? input terminal for 13.5mhz x'tal oscillation no cf2 13 o ? output terminal for 13.5mhz x'tal oscillation no eo 94 o ? output terminal for main charge pump no subpd 95 o ? output terminal for sub charge pump no fmin 90 i ? input terminal for fm vco (local oscillator) ? the signal input to this pin must be capacitor coupled ? input frequency: 10 to 150mhz please open the terminal when you do not use this terminal. moreover, please make the pull-down of this terminal effective with software. no amin 91 i ? input terminal for am vco (local oscillator) ? the signal input to this pin must be capacitor coupled ? input frequency: 0.5 to 40mhz please open the terminal when you do not use this terminal. moreover, please make the pull-down of this terminal effective with software. no hctr 92 i ? input terminal for universal counter ? the signal input to this pin must be capacitor coupled ? input frequency: 0.4 to 12mhz please open the terminal when you do not use this terminal. moreover, please make the pull-down of this terminal effective with software. no lctr 93 i ? input terminal for universal counter ? the signal input to this pin must be capacitor coupled ? input frequency: 100 to 500khz please open the terminal when you do not use this terminal. moreover, please make the pull-down of this terminal effective with software. no vreg 87 o ? internal low voltage output ? connect a bypass capacitor to this pin. (refer to page27) no note: the coupling capacitors must be placed as close to the pins as possible. a capacitance of 100pf is recommended. the capacitance value for hctr and lctr must be 1000pf or less.
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-24/31 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port options selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 n-channel open drain no 1 cmos programmable p10 to p17 p20 to p27 p30 to p35 1 bit 2 n-channel open drain programmable 1 cmos programmable pb0 to pb7 pc0 to pc7 1 bit 2 n-channel open drain programmable pe0 to pe7 pf0 to pf7 - no cmos programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no n-channel open drain no si2p0, si2p2, si2p3 pwm0, pwm1 - no cmos no si2p1 - no cmos (when selected as ordinary port) n-channel open drain (when sio2 data is selected) no fmin, amin, hctr, lctr - no input only no eo, subpd - no output only no xt1 - no input only no xt2 - no output for 32.768khz quartz oscillator n-channel open drain (when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). *1: make the following connection to minimize the noise input to the v dd 1 pin and prolong the backup time. be sure to electrically short the v ss 1, v ss 2, av ss and v ss 4 pins. example 1: when backup is active in the hold mode, the high level of the port outputs is supplied by the backup capacitors. power supply v ss 1 back-up capacitor v ss 2av ss av dd v dd 2 v dd 1 lsi v dd 4 v ss 4 vreg
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-25/31 example 2: the high level output at the ports is unstable when the hold mode.backup is in effect. power supply v ss 1 back-up capacitor v ss 2av ss a v dd v dd 2 v dd 1 lsi v dd 4 v ss 4 vreg
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-26/31 v dd 1, v ss 1 terminal condition it is necessary to place capacitors between v dd 1 and v ss 1 as describe below. ? place capacitors as close to v dd 1 and v ss 1 as possible. ? place capacitors so that the length of each terminal to th e each leg of the capacitor be equal (l1 = l1?, l2 = l2?). ? place high capacitance capacitor c1 and low capacitance capacitor c2 in parallel. ? capacitance of c2 must be more than 0.1 f. ? please mount a suitable capacitor about c1. ? use thicker pattern for v dd 1 and v ss 1. av dd , av ss terminal condition it is necessary to place capacitors between av dd and av ss as describe below. ? place capacitors as close to av dd and av ss as possible. ? place capacitors so that the length of each terminal to the each leg of the capac itor be equal (l3 = l3?). ? capacitance of c3 must be more than 1 f. ? use thicker pattern for av dd and av ss . v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 av ss av dd l3? l3 c3
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-27/31 vreg, av ss terminal condition it is necessary to place capacitors between vreg and av ss as describe below. ? place capacitors as close to vreg and av ss as possible. ? place capacitors so that the length of each terminal to the each leg of the capac itor be equal (l4 = l4?). ? capacitance of c4 must be more than 1 f to 10 f. ? use thicker pattern for vreg and av ss . v dd x, v ss x terminal condition x=2, 4 ? it is necessary to place capacitors between v dd x and v ss x as describe below. ? place capacitors as close to v dd x and v ss x as possible. ? place capacitors so that the length of each terminal to the each leg of the capac itor be equal (l5 = l5?). ? capacitance of c5 must be more than 0.1 f. ? use thicker pattern for v dd x and v ss x. (note) select c res and r res value to assure that reset is generated after the v dd becomes higher than the minimum operating voltage. recommended value c res : 0.47 f r res : 270k figure 1 reset circuit av ss vreg l4? l4 c4 v ss x v dd x l5? l5 c5 c res v dd r res res
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-28/31 figure 2 serial input/output test condition figure 3 pulse input timing condition sioclk: datain: dataout: di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0, 2) sioclk: datain: dataout: tsck tsckl tsckh tsdi thdi tddo sioclk: datain: dataout: tddo tsdi thdi tsckl tsckha data ram transmission period (only sio0, 2) tpil tpih
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-29/31 concerning differences of the m ask version and the flash version 1) although the electrical specifications are the same for the mask and flash ve rsions, differences may arise in the actual values for threshold level of the input ports, ou tput current of the output ports, input sensitivity, etc. variations may also be found from lot to lot. it must therefore be kept in mind that if finished products are designed using the actual values of the samples, these variatio ns may prevent the finished products from operating. 2) the undesirable radiation level is not listed among th e specifications. since differences may arise between the mask and flash versions, this must be kept in mind when designing the finished products. concerning differences of rom wr iting in our company and user rom writing in out company rom writing in user name of articles lc87f83c8a-fxxxx-e lc87f8396a-fxxxx-e lc87f8364a-fxxxx-e LC87F83C8AU-qip-e lc87f8396au-qip-e lc87f8364au-qip-e tape out necessary unnecessary data confirmation after writing our company user terminal destruction confirmation after writing our company user terminal curved confirmation after writing our company user the w87f83256q circuit board must be requested as the data writing board. the af-9708 made by ando is recommended as the rom writer. confirm rom writer's version to the office. method of ordering rom when rom writing by our company is done please submit program of flash rom and flash rom order material to the person in charge of each business. condition before it mounts 1. writing by user 2. writing by our company prom unwriting shipment goods prom writing shipment goods it is recommended to mount according to please mount according to the following procedures. the following procedures. recommended screening procedure no energizing temperature leaving 1505 c, 24 hr +1 -0 program reading mounting qip sample program writing /verify qip sample mounting
lc87f83c8a/c8au/96a/96au/64a/64au no.a1780-30/31 example of writing data onto the on-chip flash rom of the LC87F83C8AU/96au/64au (using the af-9708) i. writing the data using the af-9708 (made by ando) prom programmer 1. romtype settings romtype select [maker] set select [sanyo] set select [lc87f83c8a] set it corresponds now prom programmer af-9708 (made of ando). please inquire of the person in charge of each business. 2. start/stop address settings function 1 : address setting mode type no. rom capacity stop address lc87f8364au 64kb lc87f8396au 96kb LC87F83C8AU 128kb 1ffff 3. executing data erasure device b set : for data erasure execution. 4. executing data writing device f set : for program and verify execution. ii. writing board the writing board is shown in the figure below. the position of pin 1 must checked before connecting to the eprom programmer. to be used for the general-purpose eprom programmer: model w87f83256q eprom programmer 1pin LC87F83C8AU/96au/64au 1pin
lc87f83c8a/c8au/96a/96au/64a/64au ps no.a1780-31/31 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of february, 2 011. specifications and information herein are subject to change without notice.

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